The present invention relates to a current control device, and more specifically to a current control device capable of reducing a standby current of a semiconductor memory device and a turn-on current of a transistor.
With the development of computing systems and information communication technology, semiconductor memory devices for storing information therein have been rapidly developed to be manufactured with lower costs and to have smaller sizes and larger capacitance. In addition, as demand for the reduction of energy consumption also increases, semiconductor devices have been developed to restrict unnecessary current consumption.
Generally, a cell array of a dynamic random access memory (DRAM) device includes a plurality of cells coupled to word lines and bit lines that are interconnected in the form of a net. Each cell includes one NMOS transistor and one capacitor.
Operations of a general DRAM device will hereinafter be described in detail.
First, a row strobe signal (/RAS) for operating the DRAM device is activated to a low level, so that row address signals are input to a row address buffer. A row decoding operation for selecting one of word lines contained in the cell array is carried out by decoding the row address signals.
In this case, the data of cells coupled to the selected word line is applied to a pair of bit lines BL and /BL composed of a bit line and its complementary bit line. A sense-amplifier (also called a sense-amp) enable signal indicating an operation start time of a sense amplifier is enabled to drive a sense-amp driving circuit of a cell block selected by the row address signals.
After that, sense-amp bias potentials are transitioned to a core potential Vcore and a ground potential Vss by the sense-amp driving circuit, so that the sense amplifier is driven. If the sense amplifier starts its operation, voltages of the bit lines BL and /BL that have maintained a slight potential difference therebetween are transitioned to have a high potential difference therebetween.
Thereafter, a column decoder turns on a column transfer transistor that transfers data from each bit line to data bus lines in response to column address signals, such that data stored in the pair of bit lines BL and /BL is output to the outside of the semiconductor memory device through the data bus lines DB and /DB.
FIG. 1 illustrates a signal processing circuit diagram of a typical semiconductor memory device.
Referring to FIG. 1, the signal processing circuit includes a NAND gate ND1 and a plurality of inverters IV1˜IV4.
The NAND gate ND1 performs a logic NAND operation on a trigger signal TRIGGER and a set signal SET and outputs the NAND operation result. The inverters IV1˜IV4 drive an output signal of the NAND gate ND1 and output an output signal OUT.
The typical semiconductor memory device may further include a variety of circuit elements, for example, a NOR gate, a transistor, etc.
The typical semiconductor memory device may be implemented as a user-desired semiconductor memory device by a combination of an inverter, a NAND gate, a NOR gate, and a transistor.
In the typical semiconductor memory device, an inverter, a NAND gate, a NOR gate, a tri-state gate, etc. are implemented on the basis of transistors. A multi-input circuit is constructed using a combination of an AND gate and an OR gate.
For example, as can be seen from FIG. 1, an AND circuit composed of a two-input NAND gate, e.g., ND1, and a plurality of inverters, e.g. IV1˜IV4, outputs a high-level output signal OUT when two inputs are high in level.
In this case, the two input signals SET and TRIGGER may be input at the same time. However, if the set signal SET is first input to set the circuit to a set status, an output time of the output signal OUT may be determined by the trigger signal TRIGGER that is input after the set signal SET. In other words, each circuit logic has been designed to include the set signal SET and the trigger signal TRIGGER. A general circuit logic may be classified into one case in which a circuit enters an idle status upon receiving a set signal SET for setting the circuit and the other case in which the set signal SET and an idle entry signal are separated from each other.
If the semiconductor memory device enters the idle status as a user-desired operation is completed or if the semiconductor memory device such as a DRAM device enters a current reduction status such as a power-down mode, some transistors contained in an inverter circuit may maintain a turn-on status, or an off-leakage current may be generated in some other transistors.
The above-mentioned semiconductor memory device has been designed to unnecessarily consume the off-leakage current and/or the transistor turn-on current during the idle status and/or the power-down mode.
Numerous inverters have been used in most circuits. Accordingly, the off-leakage current and the transistor turn-on current may be unnecessarily consumed in, e.g., a circuit using an inverter having a large width, a delay circuit, and a delay chain.